Microsoft security update for CVE-2026-45944 — azl3 kernel
🔗 CVE IDs covered (1)
📋 Microsoft's advisory
EchelonGraph does not copy Microsoft's advisory page: its FAQ and remediation text are not shown here. Read the advisory on https://msrc.microsoft.com/update-guide/vulnerability/CVE-2026-45944. This page also shows what EchelonGraph holds for CVE-2026-45944, with the description from its CVE record, which the CVE Numbering Authority that assigned the CVE wrote: for a CVE Microsoft assigned, often in the words of Microsoft's own advisory.
🎯 Affected products10
- azl3 kernel 6.6.139.1-1 on Azure Linux 3.0
- azl3 kernel 6.6.141.1-1 on Azure Linux 3.0
- azl3 kernel 6.6.143.1-1 on Azure Linux 3.0
- azl3 kernel 6.6.144.1-1 on Azure Linux 3.0
- azl3 kernel 6.6.145.2-1 on Azure Linux 3.0
- azl3 kernel 6.6.150.1-1 on Azure Linux 3.0
- azl3 kernel 6.6.152.1-1 on Azure Linux 3.0
- azl3 kernel 6.6.157.1-1 on Azure Linux 3.0
- azl3 kernel 6.6.159.1-1 on Azure Linux 3.0
- azl3 kernel 6.6.161.1-1 on Azure Linux 3.0
✅ Updates Microsoft lists: 1 update
1 row: one per KB article or update, update type and fixed build. Their details are on Microsoft's advisory.
| KB article | Update | Fixed build |
|---|---|---|
| — | Security Update | — |
🧭 EchelonGraph on CVE-2026-45944
- EchelonGraph score
- 7.5 HIGH
- CISA KEV
- Not listed
- Fix status
- A fix is available — apply it.
Description from the CVE record (CVE.org), as published by its numbering authority
In the Linux kernel, the following vulnerability has been resolved: iommu/vt-d: Clear Present bit before tearing down context entry When tearing down a context entry, the current implementation zeros the entire 128-bit entry using multiple 64-bit writes. This creates a window where the hardware can fetch a "torn" entry — where some fields are already zeroed while the 'Present' bit is still set — leading to unpredictable behavior or spurious faults. While x86 provides strong write ordering, the compiler may reorder writes to the two 64-bit halves of the context entry. Even without compiler reordering, the hardware fetch is not guaranteed to be atomic with respect to multiple CPU writes. Align with the "Guidance to Software for Invalidations" in the VT-d spec (Section 6.5.3.3) by implementing the recommended ownership handshake: 1. Clear only the 'Present' (P) bit of the context entry first to signal the transition of ownership from hardware to software. 2. Use dma_wmb() to ensure the cleared bit is visible to the IOMMU. 3. Perform the required cache and context-cache invalidation to ensure hardware no longer has cached references to the entry. 4. Fully zero out the entry only after the invalidation is complete. Also, add a dma_wmb() to context_set_present() to ensure the entry is fully initialized before the 'Present' bit becomes visible.
Published by kernel.org, the CVE Numbering Authority that assigned CVE-2026-45944, in its CVE record at CVE.org; reused under the CVE Program's Terms of Use (its licence and MITRE's copyright notice are in our Terms of Service).