Microsoft security update for CVE-2026-45894 — azl3 kernel
🔗 CVE IDs covered (1)
📋 Microsoft's advisory
EchelonGraph does not copy Microsoft's advisory page: its FAQ and remediation text are not shown here. Read the advisory on https://msrc.microsoft.com/update-guide/vulnerability/CVE-2026-45894. This page also shows what EchelonGraph holds for CVE-2026-45894, with the description from its CVE record, which the CVE Numbering Authority that assigned the CVE wrote: for a CVE Microsoft assigned, often in the words of Microsoft's own advisory.
🎯 Affected products10
- azl3 kernel 6.6.139.1-1 on Azure Linux 3.0
- azl3 kernel 6.6.141.1-1 on Azure Linux 3.0
- azl3 kernel 6.6.143.1-1 on Azure Linux 3.0
- azl3 kernel 6.6.144.1-1 on Azure Linux 3.0
- azl3 kernel 6.6.145.2-1 on Azure Linux 3.0
- azl3 kernel 6.6.150.1-1 on Azure Linux 3.0
- azl3 kernel 6.6.152.1-1 on Azure Linux 3.0
- azl3 kernel 6.6.157.1-1 on Azure Linux 3.0
- azl3 kernel 6.6.159.1-1 on Azure Linux 3.0
- azl3 kernel 6.6.161.1-1 on Azure Linux 3.0
✅ Updates Microsoft lists: 1 update
1 row: one per KB article or update, update type and fixed build. Their details are on Microsoft's advisory.
| KB article | Update | Fixed build |
|---|---|---|
| — | Security Update | — |
🧭 EchelonGraph on CVE-2026-45894
- EchelonGraph score
- 7.8 HIGH
- CISA KEV
- Not listed
- Fix status
- A fix is available — apply it.
Description from the CVE record (CVE.org), as published by its numbering authority
In the Linux kernel, the following vulnerability has been resolved: iommu/vt-d: Clear Present bit before tearing down PASID entry The Intel VT-d Scalable Mode PASID table entry consists of 512 bits (64 bytes). When tearing down an entry, the current implementation zeros the entire 64-byte structure immediately using multiple 64-bit writes. Since the IOMMU hardware may fetch these 64 bytes using multiple internal transactions (e.g., four 128-bit bursts), updating or zeroing the entire entry while it is active (P=1) risks a "torn" read. If a hardware fetch occurs simultaneously with the CPU zeroing the entry, the hardware could observe an inconsistent state, leading to unpredictable behavior or spurious faults. Follow the "Guidance to Software for Invalidations" in the VT-d spec (Section 6.5.3.3) by implementing the recommended ownership handshake: 1. Clear only the 'Present' (P) bit of the PASID entry. 2. Use a dma_wmb() to ensure the cleared bit is visible to hardware before proceeding. 3. Execute the required invalidation sequence (PASID cache, IOTLB, and Device-TLB flush) to ensure the hardware has released all cached references. 4. Only after the flushes are complete, zero out the remaining fields of the PASID entry. Also, add a dma_wmb() in pasid_set_present() to ensure that all other fields of the PASID entry are visible to the hardware before the Present bit is set.
Published by kernel.org, the CVE Numbering Authority that assigned CVE-2026-45894, in its CVE record at CVE.org; reused under the CVE Program's Terms of Use (its licence and MITRE's copyright notice are in our Terms of Service).