CVE-2025-39752MediumMicrosoft CVSS 5.5CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:U/C:N/I:N/A:H

Microsoft security update for CVE-2025-39752

Published
June 3, 2026
Last Modified
—

🔗 CVE IDs covered (1)

📋 Microsoft's advisory

EchelonGraph does not copy Microsoft's advisory page: its FAQ and remediation text are not shown here. Read the advisory on https://msrc.microsoft.com/update-guide/vulnerability/CVE-2025-39752. This page also shows what EchelonGraph holds for CVE-2025-39752, with the description from its CVE record, which the CVE Numbering Authority that assigned the CVE wrote: for a CVE Microsoft assigned, often in the words of Microsoft's own advisory.

🎯 Affected products2

  • azl3 kernel 6.6.96.2-2 on Azure Linux 3.0
  • cbl2 kernel 5.15.186.1-1 on CBL Mariner 2.0

✅ Updates Microsoft lists: 2 updates

2 rows: one per KB article or update, update type and fixed build. Their details are on Microsoft's advisory.

KB articleUpdateFixed build
—Security Update6.6.104.2-1
—Security Update5.15.200.1-1

🧭 EchelonGraph on CVE-2025-39752

EchelonGraph score
5.5 MEDIUM
CISA KEV
Not listed
Fix status
A fix is available — apply it.

Description from the CVE record (CVE.org), as published by its numbering authority

In the Linux kernel, the following vulnerability has been resolved: ARM: rockchip: fix kernel hang during smp initialization In order to bring up secondary CPUs main CPU write trampoline code to SRAM. The trampoline code is written while secondary CPUs are powered on (at least that true for RK3188 CPU). Sometimes that leads to kernel hang. Probably because secondary CPU execute trampoline code while kernel doesn't expect. The patch moves SRAM initialization step to the point where all secondary CPUs are powered down. That fixes rarely hangs on RK3188: [ 0.091568] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000 [ 0.091996] rockchip_smp_prepare_cpus: ncores 4

Published by kernel.org, the CVE Numbering Authority that assigned CVE-2025-39752, in its CVE record at CVE.org; reused under the CVE Program's Terms of Use (its licence and MITRE's copyright notice are in our Terms of Service).

🔗 References (2)